1. Field of the Invention
This invention relates generally to a system and method for testing interrupt control and processing logic in a data processing system; and more specifically, relates to a system and method for selectively injecting interrupts on an instruction-by-instruction basis utilizing dedicated hardware bits included within each machine executable instruction.
2. Description of the Prior Art
Testing of many of today's electronic systems occurs before the actual design is built and hardware is available. Such testing is performed on a model of the design, and is commonly referred to as design simulation. During simulation, a model of the design under test is loaded onto a simulation system such as the Leapfrog Simulation System commercially available from the Cadence Corporation. The model of the design is typically described in a design language such as that known as Very High-Level Design Language (VHDL). Software programs are written which include the same instruction codes that are executed on the actual hardware. These programs are executed on the simulation system to determine if the design which is loaded on the system operates in the manner expected.
Simulating the design in the above-described manner allows problems to be discovered before the design is actually fabricated within silicon devices. This is becoming increasingly more important as the density and cost of silicon devices continues to increase. Fixing even a single design problem after the design has been fabricated within a high-density silicon device is extremely expensive, and can also greatly increase the time needed to bring a product to market.
Writing simulation programs to adequately test the logic is a challenging task. The programmer must understand the various complexities within the hardware, then work backward to devise a set of tests which will exercise these complexities to ensure proper operation of the design. This task is most difficult for those portions of a logic design having a large number of logical states, or for those circuit designs in which state changes are initiated by asynchronously occurring stimulus. In these instances, a large number of test cases must be devised to adequately exercise the entire design.
Within medium-scale and large-scale data processing systems, one of the most difficult areas of logic to simulate has historically been the instruction processor (IP) interrupt-handling, logic for both of the above-mentioned reasons. Interrupt-handling logic is the logic which handles interrupt events. These events temporarily cause an instruction processor to suspend execution of the currently executing instruction stream so that processing can be initiated on a different task. When this new task is completed, the processor may resume execution of the original instruction stream. Interrupts may occur as the result of a fault occurring within the original instruction stream, or may be the result of an entirely unrelated non-fault event such as the indication by a peripheral device of an occurrence that requires handling by the processor. Because of the varied nature and asynchronous occurrence of the interrupt events, a large number of test cases must be devised to entirely exercise the interrupt logic during simulation.
In addition to the afore-mentioned problems, testing is further complicated by the complexity associated with the interrupt handling logic. This is especially true in large-scale systems having pipelined instruction processors. Pipelined instruction processors allow multiple instructions to be in various stages of execution within the so-called "instruction pipeline" of the processor at one time. When an interrupt occurs, some, or all, of these instructions should be allowed to complete as dictated by the interrupt type. This allows the instruction processor to reach a known state before execution on a new instruction stream is initiated. The state of the processor is saved, the address for the new instruction stream is calculated, and execution is initiated on the new instruction stream. The specific logic sequences which are executed to perform these tasks are, in many cases, dependent on the type of interrupt which occurred, and are also based on which instructions and instruction combinations were executing within the instruction processor when the interrupt was received.
In the development of prior art large-scale data processing systems, thorough simulation of the interrupt handling logic requires that simulation programs be developed to simulate both fault and non-fault interrupts occurring during the execution of each instruction and each instruction combination existing within a data processing system. These simulation programs must control the number of, and type of, instructions residing within the instruction pipeline when an interrupt is induced. In addition, some of the simulation programs must initialize large portions of the data processing system to a known predetermined state before it is possible to induce an interrupt. Because of these complexities, simulation of the interrupt handling logic is a time-consuming and error-prone task. Many errors associated with the interrupt handling logic are not discovered during simulation and have to be corrected after actual hardware availability, increasing development costs. Therefore, what is needed is an improved system for exercising the interrupt logic of a complex data processing system in a manner which will allow design testing to be completed more quickly and more thoroughly. This test mechanism should provide a mechanism to exercise the logic design both during design simulation, and after actual hardware availability.